1. Field of the Invention
The present invention relates to sigma-delta modulators and dynamic element matching methods thereof, and more particularly, to continuous-time sigma-delta modulators using dynamic element matching (DEM) having low latency and dynamic element matching methods thereof.
2. Description of the Prior Art
Please refer to FIG. 1, which is a diagram of a conventional continuous-time sigma-delta modulator 100 using dynamic element matching (DEM). As shown in FIG. 1, the continuous-time sigma-delta modulator 100 includes a frequency response module 102, a quantizer 104, a DEM module 106, a digital-to-analog (DAC) converter 108, an adder 110, and a digital low-pass filter (LPF) 112. A first continuous-time signal x(t) is received at a first input terminal of the adder 110 as a resource signal, whereas a second continuous-time signal y(t) is inputted at a second input terminal of the adder 110 for compensating possible errors in the first continuous-time signal x(t). A continuous-time signal q(t) generated by the frequency response module 102 is sampled by the quantizer 104 according to a clock signal ck inputted to the quantizer 104 as well. The DEM module 106 is responsible for moving mismatches in a digital output signal of the quantizer 104 to high frequencies so that in a next term of the loop shown in FIG. 1, the mismatches are filtered off by the digital low-pass filter 112 along with related noises. Note that an input signal and an output signal of the DEM module 106 are both digital so that the DAC converter 108 is responsible for transforming the digital output signal of the DEM module 106 into an analog feedback signal, i.e., the second continuous-time signal y(t). Note that the digital low-pass filter 112 helps in noise shaping and down sampling of the output signals of the quantizer 104.
Please refer to FIG. 2, which is a waveform diagram for illustrating an excess loop delay of the analog feedback signal y(t) from the DAC converter 108 shown in FIG. 1. Within a single term of the clock signal ck, a limited time slot has to be reserved for both the quantizer 104 and the DEM module 106 so that an excess loop delay appears in the analog feedback signal y(t).
Please refer to FIG. 3, which is a waveform diagram of the DAC converter 108 shown in FIG. 1 while the DAC converter 108 is implemented with a non-return-to-zero (NRZ) DAC converter. Note that output signal of the DAC converter 108 cannot be zero, as shown in FIG. 3, and have to be applied throughout a whole cycle of the clock signal ck. Therefore, if a time slot has to be reserved for the DEM module 106, the same excess loop delay must appear. Moreover, within a same cycle of the clock signal ck, the output signal of the DAC converter 108 has to be outputted to the adder 110 in a feedback manner as soon as the digital output signal of the quantizer 104 is generated so that the time slot reserved for the DEM module 106 is not available. Otherwise, the excess loop delay shown in FIG. 3 will significantly increase a loop order and incur instability of the continuous-time sigma-delta modulator 100. It indicates a fact that implementing the DAC converter 108 with an NRZ DAC converter must face a tradeoff between loop stability of the continuous-time sigma-delta modulator 100 and an available latency reserved for the DEM module 106.
Please refer to FIG. 4, which is a waveform diagram of the DAC converter 108 shown in FIG. 1 while the DAC converter 108 is implemented with a return-to-zero (RZ) DAC converter. As shown in FIG. 4, and compared to as shown in FIG. 3, since the output signal of the DAC converter 108 may be zero at some times, a required duration of the DAC converter 108 may be cut off before a single cycle of the clock signal ck ends so that an available latency may be reserved for the DEM module 106. Since a conventional sigma-delta modulator uses over-sampling, a related sampling frequency must be high so that a length of the cycle of the clock signal ck must be short, and therefore, the available latency of the DEM module 106 must be as shorter as it can be.
The DEM module 106 is used for balancing a used probability of DAC units of the DAC converter 108. Please refer to FIG. 5, which is a schematic diagram for illustrating how the DEM module 106 works on balances between the DAC units of the DAC converter 108. Nate that codes including code(1), code(2), . . . , and code(6) are assumed to be inputted into the DAC converter 108 in turn. A number of filled fields in each row stands for a number of bits filled at a time t so that the term code(t)=n indicates that n bits should be disposed into the row of the time t. As can be observed from FIG. 5, in each column corresponding to a specific DAC unit, each DAC unit is merely used 2 or 3 times during the codes are inputted into the DAC converter 108 since the bits in the codes are filled in the DAC units in a shuffled and uniform manner. As a result, long-term probabilities of the DAC units being used are close to equal with each other. If the DEM module 106 is not applied on the DAC converter 108, mismatches between the DAC units will limit a linearity of the continuous-time sigma-delta modulator 100, and it indicates the reason why the DEM module 106 should be applied for cooperating with the DAC converter 108.
Please refer to FIG. 6, which is a schematic diagram for illustrating how DEM techniques shown in FIG. 5 work in the continuous-time sigma-delta modulator 100 shown in FIG. 1. Note that in the tables listed in FIG. 6, each column of the bits stands for a specific code having a value between 0 and 3, whereas each column stands for a specific bit in one comparator of the quantizer 104. Please refer to the codes, which have not been processed by the DEM module 106 and are listed in the left table, bits in the codes are all filled in an order of comparators A, B, and C so that a DAC unit in the DAC converter 108 corresponding to the comparator A must be most frequently used than other DAC units. The DEM module 106 arranges the bits in the codes as follows: (1) For the term Code(1)=0, no bits have to be placed; (2) For the term Code(2)=2, two bits are placed corresponding to A′ and B′ in turn; (3) For the term Code(3)=1, one bit is placed corresponding to C′ next to B′ since the ending bit in the last code Code(2) is placed corresponding to B′; (4) For the term Code(4)=3, three bits are placed corresponding to A′ (Note that A′ is cyclically next to C′), B′, and C′ in turn since the ending bit in the last code Code(3) is placed corresponding to C′; and (5) For the term Code(5)=2, two bits are placed corresponding to A′ (Note that A′ is cyclically next to C′) and B′ in turn since the ending bit in the last code Code(4) is placed corresponding to B′. As can be observed from the right table shown in FIG. 6, after arranging the bits in the codes by the DEM module 106, the used probabilities corresponding to A′, B′, and C′ are balanced with respect to those in the left table shown in FIG. 6.
However, the output signals from the DEM module 106 are inputted to the DAC converter 108 at a same cycle of the clock signal ck with raw data (i.e., the codes in the left table shown in FIG. 6) generated from the comparators A, B, C of the quantizer 104. Therefore, the excess loop delay may be generated so that errors occur in the DAC converter 108.